This application claims priority from Korean Patent Application No. 10-2002-81737 filed Dec. 20, 2002, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to reducing the occurrence of glitches during switching and in particular reducing the occurrence of glitches during switching when using differential charge pumps and phase locked loops.
2. Description of the Related Art
A phase locked loop (PLL) is a circuit for generating a clock signal with a phase which is equal to that of an input signal or leads the input signal by a predetermined amount.
FIG. 1 is a block diagram of a conventional phase locked loop. Referring to FIG. 1, the PLL 100 includes a phase-frequency detector (PFD)10, a charge pump 20, a low pass filter 30, and a voltage controlled oscillator (VCO) 40.
The phase-frequency detector 10 receives a reference clock signal CREF and a feedback clock signal FVCO and outputs a phase error signal UP or DOWN corresponding to a phase difference between the two signals CREF and FVCO. UP corresponds to a forward phase difference of one signal relative to the other signal (chosen as the reference signal). DOWN corresponds to a backward phase difference of one signal with respect to the chosen reference signal.
When a switch S1 is turned on in response to the signal UP, the charge pump 20 charges capacitors C1 and C2 of the low pass filter 30, which can be coupled to an output terminal VCP. When a switch S2 is turned on, in response to the signal DOWN, the charge pump 20 discharges the charges from the capacitors C1 and C2 to a ground voltage.
The voltage controlled oscillator VCO 40 outputs a clock signal CVCO, having a frequency which is proportional to a voltage of the output terminal VCP of the charge pump 20, to a predetermined internal circuit and a frequency divider 50.
The frequency divider 50 outputs the clock signal CVCO to the phase-frequency detector 10 or divides the clock signal CVCO by a predetermined ratio and outputs the result to the phase-frequency detector 10. However, noise in the voltage of the output terminal VCP of the charge pump 20 causes jitter in the clock signal CVCO of the voltage controlled oscillator 40.
For example, when a voltage of the output terminal VCP of the charge pump 20 is 1V, the voltage controlled oscillator 40 generates a clock signal CVCO of 200 MHz and has a frequency gain of 50 MHz/V, if 100 mV noise is input to the output terminal VCP of the charge pump 20, the clock signal CVCO of the voltage controlled oscillator 40 varies within the range of 200 MHz±5 MHz.
Accordingly, a circuit using the clock signal CVCO of the voltage controlled oscillator 40 as a reference clock signal is limited by a timing margin such as a setup time or a hold time.
Also, a circuit using the clock signal CVCO of the voltage controlled oscillator 40 as a reference clock signal is liable to malfunction and is limited by the greatest operating frequency.
As a result, even if a circuit is designed using a method which minimizes noise in the voltage of the output terminal VCP of the charge pump 20, it is fundamentally difficult to reduce jitter in the output of the voltage controlled oscillator 40.